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Filter Latency
Filter Latency
The input data samples can come at clock or lower rate. Every input sample is accompanied by the
DATAI_VALID signal.
The relation between input data samples and output decimated samples is simple: upon receiving M data
samples, the filter generates an output sample. In other words the filter must obtain M fresh input samples in
order to generate another output sample. The latency is defined here as the delay between the last sample
of the group of M data samples, and the output sample, which was calculated based on the TAPS input
samples including the group. The latency is measured in input data intervals whether those are coming at
clock or lower rate, and in clock cycles:
Latency = (TAPS/M – 1) DATAI_VALID intervals + 8 clock cycles
EQ 11
When the input samples are coming at clock rate, EQ 11 simplifies:
Latency = (TAPS/M + 7) clock cycles
The latency also depends on how many hard MAC rows (columns) the filter implementation takes and a
part-dependent number of pipeline registers used to cross inter-row or column space. For convenience, the
core calculates the overall latency and prints it out during simulation. Look for the line “LATENCY = x
DATAI_VALID intervals + 8 CLK intervals”.
Any FIR filter convolves a series of data samples with a set of filter coefficients. Thus, the filter starts
generating valid results only after getting enough data samples and coefficients. Upon power-on or
swapping coefficient pages, CoreFIR holds the FIRO_VALID signal inactive until it receives TAPS data
samples.
CoreFIR v8.5 Handbook
53
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